Archive

2020

December

• December 2, 2020 » 用信息论分析排序需要多少次比较

November

• November 20, 2020 » ReedSolomon编解码数字设计回顾

2019

March

• March 26, 2019 » Montomery算法

2018

March

• March 6, 2018 » 简单实例：条件概率，事件独立，熵，互信息

2017

June

• June 15, 2017 » project log

April

• April 20, 2017 » Extended Euclid Algorithm
• April 7, 2017 » FPGA

March

• March 28, 2017 » 模板
• March 27, 2017 » 基本工具

2016

March

• March 2, 2016 » LFSR(Linear Feedback Shift Register)结构分析

2015

March

• March 14, 2015 » LR(0) Parsing实例

2014

October

• October 22, 2014 » 速度,面积,功耗永远都是折中的吗?

2013

March

• March 28, 2013 » 数字设计的成长阶梯之我见

2012

May

• May 28, 2012 » tlm_fifo的多对一，一对多连接实例
• May 11, 2012 » 用class封装verilog验证module

April

• April 16, 2012 » 《数据结构》4皇后问题的Haskell程序建模
• April 14, 2012 » 数据结构中的满二叉树遍历用Haskell建模
• April 14, 2012 » Monad初探

January

• January 21, 2012 » 最简单的callback
• January 5, 2012 » 防毛刺时钟切换电路的设计思想

2011

March

• March 9, 2011 » uvm_tlm_fifo的实现简单模型

January

• January 14, 2011 » uvm_blocking_get_port/uvm_blocking_get_export实现的简单模型
• January 13, 2011 » uvm_blocking_put_port/uvm_blocking_put_imp实现的简单模型
• January 10, 2011 » OVM Cookbook中Factory原理分析总结

2010

October

• October 27, 2010 » systemverilog语法浏览